128k x 32 static ram module cym1836 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05273 rev. ** revised march 15, 2002 features ? high-density 4-megabit sram module 32-bit standard footprint supports densities from 16k x 32 through 1m x 32 high-speed cmos srams ? access time of 15 ns low active power ? 2.6w (max.) at 20 ns smd technology ttl-compatible inputs and outputs low profile ? max. height of 0.57 in. small pcb footprint ? 0.78 sq. in. available in simm, zip format. simm suitable for vertical or angled sockets. functional description the cym1836 is a high-performance 4-megabit static ram module organized as 128k words by 32 bits. this module is constructed from four 128k x 8 srams in soj packages mounted on an epoxy laminate board with pins. four chip se- lects (cs 1 , cs 2 , cs 3 , cs 4 ) are used to independently enable the four bytes. reading or writing can be executed on individ- ual bytes or any combination of multiple bytes through proper use of selects. writing to each byte is accomplished when the appropriate chip select (cs ) and write enable (we ) inputs are both low. data on the input/output pins (i/o) is written into the memory location specified on the address pins (a 0 through a 16 ). reading the device is accomplished by taking the chip select (cs ) low while write enable (we ) remains high. under these conditions, the contents of the memory location specified on the address pins will appear on the data in- put/output pins (i/o). the data input/output pins stay at the high-impedance state when write enable is low or the appropriate chip selects are high. two pins (pd 0 and pd 1 ) are used to identify module mem- ory density in applications where alternate versions of the jedec-standard modules can be interchanged. logic block diagram pin configuration a 0 ? a 16 oe cs 3 i/o 0 ? i/o 7 zip/simm top view cs 1 cs 2 cs 4 i/o 8 ? i/o 15 i/o 16 ? i/o 23 i/o 24 ? i/o 31 17 128k x 8 sram 4 sram 4 sram 4 sram 4 pd 0 ? open pd 1 ? open 128k x 8 128k x 8 128k x 8 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 pd 0 i/o 0 i/o 1 i/o 2 i/o 3 v cc a 7 a 8 a 9 i/o 4 i/o 5 i/o 6 i/o 7 gnd pd 1 i/o 8 i/o 9 i/o 10 i/o 11 a 0 a 1 a 2 i/o 12 i/o 13 i/o 14 i/o 15 gnd a 15 cs 2 cs 4 nc oe i/o 24 i/o 25 i/o 26 i/o 27 a 3 a 4 a 5 v cc a 6 i/o 28 i/o 29 i/o 30 i/o 31 we a 14 cs 1 cs 3 a 16 gnd i/o 16 i/o 17 i/o 18 i/o 19 a 10 a 11 a 12 a 13 i/o 20 i/o 21 i/o 22 i/o 23 gnd we
cym1836 document #: 38-05273 rev. ** page 2 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 55 c to +125 c ambient temperature with power applied............................................... ? 10 c to +85 c supply voltage to ground potential ............... ? 0.5v to +7.0v dc voltage applied to outputs in high z state ............................................... ? 0.5v to +7.0v dc input voltage............................................ ? 0.5v to +7.0v selection guide 1836-15 1836-20 1836-25 1836-30 1836-35 1836-45 maximum access time (ns) 15 20 25 30 35 45 maximum operating current (ma) 760 480 480 480 480 480 maximum standby current (ma) 180 100 100 100 100 100 shaded area contains preliminary information. operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% electrical characteristics over the operating range parameter description test conditions 1836-15 1836-20, 25, 30, 35, 45 unit min. max. min. max. v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc 2.2 v cc v v il input low voltage ? 0.5 0.8 ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 20 +20 ? 20 +20 a i oz output leakage current gnd < v o < v cc , output disabled ? 20 +20 ? 20 +20 a i cc v cc operating supply current v cc = max., i out = 0 ma, cs < v il 760 480 ma i sb1 automatic cs power-down current [1] v cc = max., cs > v ih , min. duty cycle = 100% 180 100 ma i sb2 automatic cs power-down current [1] v cc = max., cs > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v 60 28 ma shaded area contains preliminary information. capacitance [2] parameter description test conditions max. unit c in input capacitance [3] t a = 25 c, f = 1 mhz, v cc = 5.0v 40/20 pf c out output capacitance 15 pf notes: 1. a pull-up resistor to v cc on the cs input is required to keep the device deselected during v cc power-up, otherwise i sb will exceed values given. 2. tested on a sample basis. 3. 20 pf on cs , 40 pf all others.
cym1836 document #: 38-05273 rev. ** page 3 of 9 ac test loads and waveforms 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) < 5ns < 5 ns output r1 481 ? r1 481 ? r2 255 ? r2 255 ? 167 ? equivalent to: th venin equivalent 1.73v
cym1836 document #: 38-05273 rev. ** page 4 of 9 switching characteristics over the operating range [4] parameter description 1836-15 1836- 20 1836-25 1836-30 1836-35 1836-45 unit min. max. min. max. min. max. min. max. min. max. min. max. read cycle t rc read cycle time 15 20 25 30 35 45 ns t aa address to data valid 15 20 25 30 35 45 ns t oha output hold from address change 3 3 3 3 3 3 ns t acs cs low to data valid 15 20 25 30 35 45 ns t doe oe low to data valid 7 8 8 10 12 15 ns t lzoe oe low to low z 0 0 0 0 0 0 ns t hzoe oe high to high z 7 8 10 11 12 15 ns t lzcs cs low to low z [5] 3 3 3 3 3 3 ns t hzcs cs high to high z [5, 6] 7 10 10 13 15 18 ns write cycle [7] t wc write cycle time 15 20 25 30 35 45 ns t scs cs low to write end 12 15 15 18 20 25 ns t aw address set-up to write end 12 15 15 18 20 25 ns t ha address hold from write end 0 0 0 0 0 0 ns t sa address set-up to write start 0 0 0 0 0 0 ns t pwe we pulse width 12 15 15 18 20 25 ns t sd data set-up to write end 7 10 10 13 15 20 ns t hd data hold from write end 0 0 0 0 0 0 ns t lzwe we high to low z 3 3 3 3 3 3 ns t hzwe we low to high z [6] 0 6 0 8 0 10 0 15 0 15 0 18 ns shaded area contains preliminary information. notes: 4. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. at any given temperature and voltage condition, t hzcs is less than t lzcs for any given device. these parameters are guaranteed by design and not 100% tested. 6. t hzcs and t hzwe are specified with c l = 5 pf as in part (b) of ac test loads and waveforms. transition is measured 500 mv from steady-state voltage. 7. the internal write time of the memory is defined by the overlap of cs low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write.
cym1836 document #: 38-05273 rev. ** page 5 of 9 switching waveforms notes: 8. we is high for read cycle. 9. device is continuously selected, cs = v il and oe = v il . 10. address valid prior to or coincident with cs transition low. previous data valid data valid t rc t aa t oha address data out read cycle no.1 [8, 9] data valid t rc t acs t doe t lzoe t lzcs high impedance t hzoe t hzcs high impedance data out oe cs read cycle no. 2 [8, 10] t wc data valid data undefined high impedance t scs t aw t sa t pwe t ha t hd t hzwe t lzwe t sd cs we address data in data out write cycle no.1 (we controlled) [7]
cym1836 document #: 38-05273 rev. ** page 6 of 9 switching waveforms (continued) note: 11. if cs goes high simultaneously with we high, the output remains in a high-impedance state. t wc data valid data undefined high impedance t scs t aw t pwe t ha t hd t hzwe t sd cs we address data in data out t sa write cycle no. 2 (cs controlled) [7, 11]] truth table cs n we oe input/outputs mode h x x high z deselect/power-down l h l data out read l l x data in write l h h high z deselect
cym1836 document #: 38-05273 rev. ** page 7 of 9 ordering information [12] speed (ns) ordering code package name package type operating range 15 CYM1836PM-15C pm03 64-pin simm module commercial cym1836pz-15c pz08 64-pin zip module cym1836py-15c pm08 64-pin gold simm module cym1836p8-15c pm04 72-pin gold simm module 20 cym1836pm-20c pm03 64-pin simm module commercial cym1836pz-20c pz08 64-pin zip module cym1836py-20c pm08 64-pin gold simm module cym1836p8-20c pm04 72-pin gold simm module 25 cym1836pm-25c pm03 64-pin simm module commercial cym1836pz-25c pz08 64-pin zip module cym1836py-25c pm08 64-pin gold simm module cym1836p8-25c pm04 72-pin gold simm module 30 cym1836pm-30c pm03 64-pin simm module commercial cym1836pz-30c pz08 64-pin zip module cym1836py-30c pm03 64-pin gold simm module cym1836p8-30c pm04 72-pin gold simm module 35 cym1836pm-35c pm03 64-pin simm module commercial cym1836pz-35c pz08 64-pin zip module cym1836py-35c pm03 64-pin gold simm module cym1836p8-35c pm04 72-pin gold simm module 45 cym1836pm-45c pm03 64-pin simm module commercial cym1836pz-45c pz08 64-pin zip module cym1836py-45c pm03 64-pin gold simm module cym1836p8-45c pm04 72-pin gold simm module shaded area contains preliminary information. note: 12. 64-pin simm suitable for use in angled simm applications. package diagrams 64-pin simm module pm03 3.855 max. 3.580/3.588 124/.126 dia. 2plcs .397/.403 .245/.255 pin 1 .075/.085 .249/.251 .061/.063 r .135 ref. .595 max. . 200 max. 128kx8 128kx8 128kx8 128kx8
cym1836 document #: 38-05273 rev. ** page 8 of 9 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 72-pin plastic simm module pm04 64-pin zip module pz08
cym1836 document #: 38-05273 rev. ** page 9 of 9 document title: cym1836 128k x 32 static ram module document number: 38-05273 rev. ecn no. issue date orig. of change description of change ** 114174 3/19/02 dsg change from spec number: 38-m-00050 to 38-05273
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